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PRODUCT PREVIEW
87C196LB CHMOS 16-BIT MICROCONTROLLER
Automotive
s 20 MHz operation s 24 Kbytes of on-chip OTPROM s 768 bytes of on-chip register RAM s Register-to-register architecture s Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines s Integrated, industry-standard J1850 communication protocol s Six-channel/10-bit A/D with sample and hold s High-speed event processor array -- Six capture/compare channels -- Two compare-only channels -- Two 16-bit software timers
s Full-duplex serial I/O port with dedicated baud-rate generator s Enhanced full-duplex, synchronous serial I/O port (SSIO) s Programmable 8- or 16-bit external bus s Optional clock doubler with programmable clock output signal s SFR register that indicates the source of the last reset s Design enhancements for EMI reduction s Oscillator failure detection circuitry s Watchdog timer (WDT) s -40 C to +125 C ambient temperature s 52-pin PLCC package
16 MHz standard; 20 MHz is speed premium
NOTE This datasheet contains information on products in the design phase of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. The 87C196LB is a high-performance 16-bit microcontroller with integrated support for the J1850 communication protocol. The 87C196LB is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices where a separate resonator was required in the past. Another costsavings feature is the fact that the I/O ports are driven low at reset, avoiding the need for pull-up resistors.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. (c) INTEL CORPORATION, 1996 February 1996 Order Number: 272807-000
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Port 2
Port 6
Port 0
J1850 Protocol Handler
Watchdog Timer
Enhanced SSIO
A/D Converter
Peripheral Addr Bus (10)
Peripheral Data Bus (16) Port 2 Memory Data Bus (16) Memory Addr Bus (16)
Bus Control
Bus Controller
AD15:0
SIO
Baud-rate Generator
Bus-Control Interface Unit Queue Microcode Engine
Peripheral Transaction Server Interrupt Controller EPA
6 Capture/ Compare Channels 2 Timers 2 Compare-only Channels
Source (16) Port 1,6 ALU Register RAM 768 Bytes Memory Interface Unit
Destination (16)
OTPROM 24 Kbytes
Two additional capture/compare channels (EPA6 and EPA7) are available as software timers. They are not connected to package pins.
A3416-01
Figure 1. 87C196LB Block Diagram
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1.0
NOMENCLATURE OVERVIEW
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8
X
X
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A2815-02
Figure 2. Product Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed Options A N 7 C 196Lx no mark 20 Description Automotive operating temperature range (-40 C to 125 C ambient) with Intel standard burn-in. PLCC OTPROM CHMOS 8XC196Lx family of products 16 MHz 20 MHz
PRODUCT PREVIEW
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2.0
PINOUT
AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 AD12 / P4.4 / PBUS.12 AD11 / P4.3 / PBUS.11 AD10 / P4.2 / PBUS.10 AD9 / P4.1 / PBUS.9 AD8 / P4.0 / PBUS.8 AD7 / P3.7 / PBUS.7 AD6 / P3.6 / PBUS.6 AD5 / P3.5 / PBUS.5 AD4 / P3.4 / PBUS.4 AD3 / P3.3 / PBUS.3 AD2 / P3.2 / PBUS.2
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47
AD15 / P4.7 / PBUS.15 P5.2 / PLLEN /WR# / WRL# P5.3 / RD# VPP VSS (core) P5.0 / ADV# / ALE VSS1 (port) XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0
AN87C196LB View of component as mounted on PC board
46 45 44 43 42 41 40 39 38 37 36 35 34
P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 VREF ANGND P0.7 / ACH7 / PMODE.3 P0.6 / ACH6 / PMODE.2 P0.5 / ACH5 / PMODE.1 P0.4 / ACH4 / PMODE.0 P0.3 / ACH3
AD1 / P3.1 / PBUS.1 AD0 / P3.0 / PBUS.0 RESET# EA# VSS1 (port) VCC P2.0 / TXD / PVER P2.1 / RXD / PALE# P2.2 / EXTINT / PROG# P2.4 / RXJ1850 / AINC# P2.6/TXJ1850 / CPVER P2.7 / CLKOUT / PACT# P0.2 / ACH2
21 22 23 24 25 26 27 28 29 30 31 32 33
A3361-01
Figure 3. 87C196LB 52-pin Package
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Table 2. 87C196LB 52-pin Package Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS1 (port) P5.0 / ADV# / ALE VSS (core) VPP P5.3 / RD# P5.2 / PLLEN / WR# / WRL# AD15 / P4.7 / PBUS.15 AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 AD12 / P4.4 / PBUS.12 AD11 / P4.3 / PBUS.11 AD10 / P4.2 / PBUS.10 AD9 / P4.1 / PBUS.9 AD8 / P4.0 / PBUS.8 AD7 / P3.7 / PBUS.7 AD6 / P3.6 / PBUS.6 AD5 / P3.5 / PBUS.5 AD4 / P3.4 / PBUS.4 Name Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name AD3 / P3.3 / PBUS.3 AD2 / P3.2 / PBUS.2 AD1 / P3.1 / PBUS.1 AD0 / P3.0 / PBUS.0 RESET# EA# VSS1 (port) VCC P2.0 / TXD / PVER P2.1 / RXD / PALE# P2.2 / EXTINT / PROG# P2.4 / RXJ1850 / AINC# P2.6 / TXJ1850 / CPVER P2.7 / CLKOUT / PACT# P0.2 / ACH2 P0.3 / ACH3 P0.4 / ACH4 / PMODE.0 P0.5 / ACH5 / PMODE.1 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Name P0.6 / ACH6 / PMODE.2 P0.7 / ACH7 / PMODE.3 ANGND V REF P1.3 / EPA3 P1.2 / EPA2 / T2DIR P1.1 / EPA1 P1.0 / EPA0 / T2CLK P6.0 / EPA8 / COMP0 P6.1 / EPA9 / COMP1 P6.4 / SC0 P6.5 / SD0 P6.6 / SC1 P6.7 / SD1 XTAL2 XTAL1
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Table 3. Pin Assignment Arranged by Functional Categories Addr & Data Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Input/Output Name P0.2 / ACH2 P0.3 / ACH3 P0.4 / ACH4 P0.5 / ACH5 P0.6 / ACH6 P0.7 / ACH7 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 P2.0 / TXD Pin 33 34 35 36 37 38 44 43 42 41 27 Pin 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 P2.2 P2.4 / RXJ1850 P2.6 / TXJ1850 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.2 P5.3 P6.0 / EPA8 / COMP0 P6.1 / EPA9 / COMP1 P6.4 / SC0 P6.5 / SD0 P6.6 / SC1 P6.7 / SD1 Input/Output (Cont'd) Name P2.1 / RXD Pin 28 29 30 31 32 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 2 6 5 45 46 47 48 49 50 Program Control Name AINC# CPVER PACT# PALE# PBUS.0 PBUS.1 PBUS.2 PBUS.3 PBUS.4 PBUS.5 PBUS.6 PBUS.7 PBUS.8 PBUS.9 PBUS.10 PBUS.11 PBUS.12 PBUS.13 PBUS.14 PBUS.15 PMODE.0 PMODE.1 PMODE.2 PMODE.3 PROG# PVER Pin 30 31 32 28 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 35 36 37 38 29 27 VCC VPP VREF VSS (core) VSS1 (port) Power & Ground Name ANGND Pin 39 26 4 40 3 1, 25 Bus Cont & Status Name ADV# / ALE CLKOUT RD# WR# / WRL# Pin 2 32 5 6 Processor Control Name EA# EXTINT PLLEN RESET# XTAL1 XTAL2 Pin 24 29 6 23 52 51
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SIGNALS
Table 4. Signal Descriptions Name Type I Analog Channels These signals are analog inputs to the A/D converter. The A/D inputs share package pins with port 0. These pins may individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. The ANGND and VREF pins must be connected for the A/D converter and port 0 to function. ACH7:2 share package pins with the following signals: ACH2/P0.2, ACH3/P0.3, ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1, ACH6/P0.6/PMODE.2, and ACH7/P0.7/PMODE.3. Description
ACH7:2
AD15:0
I/O
Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0-15 are presented on the bus and can be latched using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred. AD7:0 share package pins with P3.7:0 and PBUS.7:0; AD15:8 share package pins with P4.7:0 and PBUS.15:8.
ADV#
O
Address Valid This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An external latch can use this signal to demultiplex the address from the address/data bus. A decoder can also use this signal to generate chip selects for external memory. ADV# shares a package pin with P5.0 and ALE.
AINC#
I
Auto Increment During slave programming, this active-low input enables the auto-increment feature. (Auto increment allows reading or writing of sequential OTPROM locations, without requiring address transactions across the PBUS for each read or write.) AINC# is sampled after each location is programmed or dumped. If AINC# is asserted, the address is incremented and the next data word is programmed or dumped. AINC# shares package pins with P2.4 and RXJ1850.
ALE
O
Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. An external latch can use this signal to demultiplex the address from the address/data bus. ALE shares a package pin with P5.0 and ADV#.
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Table 4. Signal Descriptions (Continued) Name ANGND Type GND Analog Ground ANGND must be connected for A/D converter and port 0 operation. ANGND and VSS should be nominally at the same potential. CLKOUT O Output Output of the internal clock generator. You can select one of frequencies: f, f/2, or f/4. CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7 and PACT#. COMP1:0 O Event Processor Array (EPA) Compare Pins These signals are the outputs of the EPA compare-only channels. COMP1:0 share package pins with the following signals: COMP0/P6.0/EPA8 and COMP1/P6.1/EPA9. CPVER O Cumulative Program Verification During slave programming, a high signal indicates that all locations programmed correctly, while a low signal indicates that an error occurred during one of the programming operations. CPVER shares a package pin with P2.6, TXJ1850, and ONCE#. EA# I External Access This input determines whether memory accesses to special-purpose and program memory partitions are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# also controls entry into the programming modes. If EA# is at VPP voltage (typically +12.5 V) on the rising edge of RESET#, the microcontroller enters a programming mode. NOTE: Systems with EA# tied inactive have idle time between external bus cycles. When the address/data bus is idle, you can use ports 3 and 4 for I/O. Systems with EA# tied active cannot use ports 3 and 4 as standard I/O; when EA# is active, these ports will function only as the address/data bus. When EA# is active, a read or write to P3_REG, P4_REG, P3_PIN, or P4_PIN accesses the corresponding location (1FFCH, 1FFDH, 1FFEH, or 1FFFH) in external memory. Description
three
EA# is sampled and latched only on the rising edge of RESET#. Changing the level of EA# after reset has no effect. EPA9:8 EPA3:0 I/O Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. The EPA signals share package pins with the following signals: EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3, EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7:6 do not connect to package pins. They cannot be used to capture an event, but they can function as software timers. EPA5:4 are not implemented.
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Table 4. Signal Descriptions (Continued) Name EXTINT Type I External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending bit. EXTINT is sampled during phase 2. The minimum high time is one state time. In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation. The interrupt need not be enabled. If the EXTINT interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT shares a package pin with P2.2 and PROG#. P0.7:2 I Port 0 This is a high-impedance, input-only port. Port 0 pins should not be left floating. The port 0 signals share package pins with the A/D inputs. These pins may individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. ANGND and VREF must be connected for port 0 to function. P0.3:2 share package pins with ACH3:2 and P0.7:4 share package pins with ACH7:4 and PMODE.3:0. P1.3:0 I/O Port 1 This is a standard bidirectional port that shares package pins with individually selectable special-function signals. Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK, P1.1/EPA1, P1.2/EPA2/T2DIR, P1.3/EPA3. P2.7:6 P2.4 P2.2:0 I/O Port 2 This is a standard bidirectional port that shares package pins with individually selectable special-function signals. Port 2 shares package pins with the following signals: P2.0/TXD/PVER, P2.1/RXD/PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#/RXJ1850, P2.6/TXJ1850/ONCE#/CPVER, P2.7/OSCOUT/PACT#. P3.7:0 I/O Port 3 This is a memory-mapped, 8-bit, bidirectional port with programmable opendrain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers.. P3.7:0 share package pins with AD7:0 and PBUS.7:0. P4.7:0 I/O Port 4 This is a memory-mapped, 8-bit, bidirectional port with open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8 and PBUS.15:8. Description
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Table 4. Signal Descriptions (Continued) Name P5.3:2 P5.0 Type I/O Port 5 This is a memory-mapped, bidirectional port. Port 5 shares package pins with the following signals: P5.0/ADV#/ALE, P5.2/WR#/WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not implemented. P6.7:4 P6.1:0 O Port 6 This is a standard bidirectional port. Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0, P6.1/EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1. PACT# O Programming Active During auto programming or ROM-dump, a low signal indicates that programming or dumping is in progress, while a high signal indicates that the operation is complete. PACT# is multiplexed with P2.7 and OSCOUT. PALE# I Programming ALE During slave programming, a falling edge causes the device to read a command and address from the PBUS. PALE# is multiplexed with P2.1 and RXD. PBUS.15:0 I/O Address/Command/Data Bus During slave programming, ports 3 and 4 serve as a bidirectional port with open-drain outputs to pass commands, addresses, and data to or from the device. Slave programming requires external pull-up resistors. During auto programming and ROM-dump, ports 3 and 4 serve as a regular system bus to access external memory. P4.6 and P4.7 are left unconnected; P1.1 and P1.2 serve as the upper address lines. Slave programming: PBUS.7:0 share package pins with AD7:0 and P3.7:0. PBUS.15:8 share package pins with AD15:8 and P4.7:0. Auto programming: PBUS.15:8 share package pins with AD15:8 and P4.7:0; PBUS.7:0 share package pins with AD7:0 and P3.7:0. PLLEN PMODE.3:0 I I Phase-locked Loop Enable This active-high input pin enables the on-chip clock multiplier. Programming Mode Select Determines the programming mode. PMODE is sampled after a device reset and must be static while the microcontroller is operating. PMODE.3:0 are multiplexed with P0.7:4 and ACH7:4. Description
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Table 4. Signal Descriptions (Continued) Name PROG# Type I Programming Start During programming, a falling edge latches data on the PBUS and begins programming, while a rising edge ends programming. The current location is programmed with the same data as long as PROG# remains asserted, so the data on the PBUS must remain stable while PROG# is active. During a word dump, a falling edge causes the contents of an OTPROM location to be output on the PBUS, while a rising edge ends the data transfer. PROG# is multiplexed with P2.2 and EXTINT. PVER O Program Verification During slave or auto programming, PVER is updated after each programming pulse. A high output signal indicates successful programming of a location, while a low signal indicates a detected error. PVER is multiplexed with P2.0 and TXD. RD# O Read Read-signal output to external memory. RD# is asserted only during external memory reads. RD# shares a package pin with P5.3. RESET# I/O Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. After a device reset, the first instruction fetch is from 2080H. RXJ1850 I Receive This signal carries messages from an off-chip, J1850 transceiver to the integrated J1850 module. RXJ1850 shares a package pin with P2.4 and AINC#. RXD I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1 and PALE#. SC1:0 I/O Clock Pins for SSIO0 and 1 For handshaking mode, configure SC1:0 as open-drain outputs. This pin carries a signal only during receptions and transmissions. When the SSIO port is idle, the pin remains either high (with handshaking) or low (without handshaking). SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6. SD1:0 I/O Data Pins for SSIO0 and 1 These pins are the data I/O pins for SSIO0 and 1. SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7. Description
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Table 4. Signal Descriptions (Continued) Name T2CLK Type I Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature counting mode. T2CLK shares a package pin with P1.0 and EPA0. T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.2 and EPA2. TXJ1850 O Transmit This signal carries messages from the integrated J1850 module to an off-chip J1850 transceiver. TXJ1850 must not be driven high during reset and should only be used as an output. TXJ1850 shares a package pin with P2.6, ONCE#, and CPVER. TXD O Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0 and PVER. VCC VPP PWR PWR Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Programming Voltage VPP causes the device to exit powerdown mode when it is driven low for at least 50 ns. Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks, but not the internal oscillator. If you do not plan to use the powerdown feature, connect V PP to V CC. VREF VSS, VSS1 PWR GND Reference Voltage for the A/D Converter This pin supplies operating voltage to the A/D converter. Digital Circuit Ground (Core Ground, Port Ground) These pins supply ground for the digital circuitry. Connect each VSS and VSS1 pin to ground through the lowest possible impedance path. V SS pins are connected to the core ground region of the microcontroller, while VSS1 pins are connected to the port ground region. (ANGND is connected to the analog ground region.) Separating the ground regions provides noise isolation. Description
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AUTOMOTIVE
Table 4. Signal Descriptions (Continued) Name WR# Type O Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. Forcing WR# high while RESET# is low, causes the device to enter PLL-bypass mode. When the device is in PLL-bypass mode, the internal phase clocks operate at one-half the frequency of the frequency on XTAL1. WR# shares a package pin with P5.2, WRL#, and PLLEN.
Description
The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
WRL#
O
Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares package pin with P5.2, WR#, and PLLEN.
The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
I
Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.
XTAL2
O
Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
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4.0
ADDRESS MAP
Table 5. Address Map Hex Address Range FFFF 8000 7FFF 2080 207F 2000 1FFF 1FE0 1FDF 1F00 1EFF 0300 02FF 0100 00FF 0000 Description External device (memory or I/O) connected to address/data bus Program memory (internal nonvolatile or external memory); see Note 1 Special-purpose memory (internal nonvolatile or external memory) Memory-mapped SFRs Peripheral SFRs External device (memory or I/O) connected to address/data bus; (future SFR expansion; see Note 2) Upper register file (general-purpose register RAM) Lower register file (register RAM, stack pointer, and CPU SFRs) Addressing Modes Indirect or indexed Indirect or indexed Indirect or indexed Indirect or indexed Indirect, indexed, or windowed direct Indirect or indexed Indirect, indexed, or windowed direct Direct, indirect, or indexed
NOTES: 1. After a reset, the microcontroller fetches its first instruction from 2080H. 2. The content or function of these locations may change in future microcontroller revisions, in which case a program that relies on a location in this range might not function properly.
5.0
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................. -60C to +150 C Voltage from V PP or EA# to V SS or ANGND... -0.5V to +13.0 V Voltage from any other pin to V SS or ANGND ... -0.5V to +7.0V Power Dissipation .......................................................... 0.5 W
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias)...........-40C to +125C VCC (Digital Supply Voltage) ............................ 4.50V to 5.50V VREF (Analog Supply Voltage)............................ 4.50V to 5.50V FXTAL1 (Input Frequency): - PLL in 2x mode............................ 4 MHz to 10 MHz - PLL in 1x mode............................ 8 MHz to 20 MHz Notes 1. ANGND and V SS should be nominally at the same potential. 2. VREF should not exceed VCC by more than 0.5V.
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5.1
DC Characteristics
Table 6. DC Characteristics at VCC = 4.5V to 5.5V
Symbol ICC
Parameter VCC supply current (-40 C to +125 C ambient) Active mode supply current (typical) A/D reference supply current Idle mode current Powerdown mode current Input low voltage (all pins) Input high voltage (all pins) Output low voltage (outputs configured as complementary) Output high voltage (outputs configured as complementary) Input leakage current (standard inputs) Input leakage current (port 0--A/D inputs) Input high current (NMI pin, bond PAO only) Output low voltage in reset
Min
Typical 50
Max TBD
Units mA
Test Conditions (Note 4) FXTAL1 = 20 MHz, VCC = VPP = V REF = 5.5V (While device is in reset)
ICC1 IREF IIDLE IPD V IL VIH VOL
50 2 15 50 - 0.5V 0.7 VCC TBD TBD TBD 0.3 VCC VCC + 0.5 0.3 0.45 1.5 V CC - 0.3 VCC - 0.7 VCC - 1.5 8 1 +175 1
mA mA mA A V V V V V V V V A A A V (Note 7) IOL = 200 A (Notes 3, 5) IOL = 3.2 mA IOL = 7.0 mA IOH = - 200 A (Notes 3, 5) IOH = - 3.2 mA IOH = - 7.0 mA VSS VIN VCC (Note 2) VSS VIN VREF VSS VIN VCC IOL = 6 A (Notes 1, 8) FXTAL1 = 20 MHz, VCC = VPP = V REF = 5.5V VCC = VPP = V REF = 5.5V (Note 6)
VOH
ILI ILI1 IIH VOL2
NOTES: 1. All bidirectional pins except P5.1/INST and P2.7/CLKOUT which are excluded because they are not weakly pulled low in reset. Bidirectional pins include ports 1-6. 2. Standard input pins include XTAL1, EA#, RESET#, and ports 1-6 when configured as inputs. 3. All bidirectional pins when configured as complementary outputs. 4. Device is static and should operate below 1 Hz, but is only tested down to 4 MHz with the PLL enabled. With the PLL bypassed, the device is only tested down to 8MHz. 5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values are 10 mA. 6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5.5V. 7. VIH max for port 0 is V REF + 0.5V. 8. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.
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Table 6. DC Characteristics at VCC = 4.5V to 5.5V (Continued) Symbol IOL2 Parameter Output low current in reset Reset pullup resistor Output low voltage in reset (RESET# pin only) Output low voltage in reset (P2.6 only) Pin capacitance (any pin to VSS) Weak pullup resistance (approximate) 150K Min TBD TBD TBD 6K Typical Max TBD TBD TBD 65K 0.3 0.5 0.8 1 10 Units A A A V V V V pF IOL3 = 4 mA (Note 8) IOL3 = 6 mA IOL3 = 10 mA IOL4 = TBD FTEST = 1.0 MHz (Note 6) Test Conditions (Note 4) VOL2 = TBD VOL2 = TBD VOL2 = TBD
RRST V OL3
V OL4 CS RWPU
NOTES: 1. All bidirectional pins except P5.1/INST and P2.7/CLKOUT which are excluded because they are not weakly pulled low in reset. Bidirectional pins include ports 1-6. 2. Standard input pins include XTAL1, EA#, RESET#, and ports 1-6 when configured as inputs. 3. All bidirectional pins when configured as complementary outputs. 4. Device is static and should operate below 1 Hz, but is only tested down to 4 MHz with the PLL enabled. With the PLL bypassed, the device is only tested down to 8MHz. 5. Maximum IOLor IOH currents per pin will be characterized and published at a later date. Target values are 10 mA. 6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5.5V. 7. VIH max for port 0 is V REF + 0.5V. 8. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.
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5.2
AC Characteristics (Over Specified Operating Conditions)
Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FXTAL1 = 8MHz with PLL enabled in clock-doubler mode.
Table 7. AC Characteristics Symbol Parameter Min Max Units The 87C196LB will meet these specifications FXTAL1 f Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Operating frequency, f = F XTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode t TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX Period t = 1/f XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling to ALE Rising ALE Falling to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low to RD# High RD# High to ALE Rising RD# Low to Address Float ALE Low to WR# Low CLKOUT Low to WR# Falling Edge Data Valid to WR# High CLKOUT High to WR# Rising Edge WR# Low to WR# High Data Hold after WR# High t - 10 -5 t - 23 - 10 t - 20 t - 25 15 25 t - 10 t - 15 t - 40 t - 30 4 t-5 t t + 25 5 30 t - 10 - 10 - 20 4t t + 10 8.0 50 20 2t t + 15 15 15 20.0 125 110 MHz ns ns(2) ns ns ns ns ns ns ns ns ns ns ns ns(3) ns ns ns ns ns ns ns 8.0 4.0 20.0 10.0 MHz(1)
NOTES: 1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is only tested down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only.
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Table 7. AC Characteristics (Continued) Symbol TWHLH TWHAX TRHAX TAVDV TRLDV TCLDV TRHDZ TRXDX Parameter WR# High to ALE High AD15:8 Hold after WR# High AD15:8 Hold after RD# High Min t - 10 t - 30
(4)
Max t + 15
Units ns(3) ns ns
t - 30(4)
The system must meet these specifications to work with the 87C196LB Address Valid to Input Data Valid RD# Low to Input Data Valid CLKOUT Low to Input Data Valid RD# High to Input Data Float Data Hold after RD# Inactive 0 3t - 55 t - 22 t - 50 t ns ns ns ns ns
NOTES: 1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is only tested down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only.
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6.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 8. Thermal Characteristics Package Type AN87C196LB (52-pin PLCC) JA 42C/W JC 15C/W
NOTES: 1. JA = Thermal resistance between junction and the surrounding environment (ambient). Measurements are taken 1 ft. away from case in static air flow environment. JC = Thermal resistance between juction and package surface (case). 2. All values of JA and JC may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. Typical variations are 2C/W. 3. Values listed are at a maximum power dissipation of 0.50 W.
7.0 DESIGN CONSIDERATIONS
To be supplied.
8.0
DEVICE ERRATA
There is no known device errata at this time.
9.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with an "A" at the end of the topside field process order (FPO) number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices.
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